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SmartSwitch
LCD 36 x 24 Display
BLOCK DIAGRAM & PIN CONFIGURATIONS FOR RGB LEDS
TM
1
4
V LC
V DD
36 x 24 Dot Matrix
LCD Panel
seg1 seg36
9
6
FLM
SCP
Timing Control
Segment Driver
7
5
3
LP
Din
GND
40bit Latch
CK
CK 40bit
D Shift Register Q
11
Dout
IS01BFRGB
RGB LED Option and
Black and White LCD Mode
E
Red
8
BL-LED (–)
10
BL-LED (+)
Green
Blue
2
12
BL-LED (–)
BL-LED (–)
Pin No.
1
2
3
4
5
Symbol
V LC
BL-LED (–)
GND
V DD
Din
Name
Power
Terminal of Backlight LED
Ground
Power
Data Input
Function
Power source for LCD drive
Cathode for green
Power source for logic circuit
Display serial data bit. Note: to map the display data, because of the difference between the
number of internal shift register data (40) and the single line of LCD pixels (36), the first four
bits of data shifted will be dummy bits.
6
SCP
Serial Clock Pulse
Clock used by 40-bit internal shift register of the switch, shifting the display data bit presented
at Din at falling edge.
7
8
9
10
11
12
LP
BL-LED (–)
FLM
BL-LED (+)
Dout
BL-LED (–)
Latch Pulse
Terminal of Backlight LED
First Line Marker
Terminal of Backlight LED
Data Output
Terminal of Backlight LED
Line data latch pulse will latch content of internal 40-bit shift register at falling edge for one
line of display. LP will also increment the display line by one.
Cathode for red
The marking signal for the first line data of LCD display. The first line of LCD will be selected
by the falling edge of LP signal during the high level (FLM).
Anode for common
Display serial output. Can be used to connect to Din of the next SMARTDISPLAY. As a result,
many SMARTDISPLAYS can be controlled with one clock and data signal.
Cathode for blue
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